1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having field effect transistors.
2. Description of the Related Art
The demands for improved performance for semiconductor devices such as memory LSIs have been on the upswing year after year especially with the recent developments of data communication apparatuses. Efforts to improve on transistor high-speed operation continue. This effort has also been ongoing for the peripheral circuit such as memory LSIs, CPUs and arithmetic and logical units, for example, to speed up n- and p-channel field effect transistors used in the peripheral circuit. Speeding up of the operation has been made mainly through miniaturization of the structure of semiconductor elements and backed up by the advancement of lithography techniques for forming semiconductor elements.
However, the minimum lithography size (minimum gate lithography size) presently required is equal to or longer than the wavelength of light used by lithography and, also, finer patterning is becoming difficult.
In order to overcome this difficulty and speed up the operation of field effect transistors, a method has been proposed by which strain is applied to silicon in the channel of a field effect transistor. According to a method disclosed in JP-A-11-340337, by utilizing the phenomenon that an electron mobility (effective mass) changes if strain is applied to silicon crystal, silicon germanium having a larger lattice constant than silicon, used as the material of an underlying film on which a field effect transistor is to be formed, and a silicon layer, epitaxially formed on the underlying layer to apply strain to silicon in a channel region, raise the mobility and speed up the operation of the transistor.
As one approach to speeding up the operation of field effect transistors of a recent semiconductor device, the above-described method has been studied with which silicon germanium material, having a larger lattice constant than silicon, is used as the material of an underlying film for silicon in the channel region to apply strain to the silicon and raise the mobility.
This method is, however, associated with the following problems and is no longer deemed practical. If material having a different lattice constant is epitaxially grown so as to obtain lattice matching, the energy of strain applied to the crystal becomes large and crystal dislocation occurs in the silicon film having a thickness equal to or greater than a critical film thickness. If silicon germanium not commonly used is introduced, it is necessary to use a new manufacture system for processes of manufacturing semiconductor devices such as LSIs and the manufacture cost rises.
Speeding up the operation of transistors is essential for a semiconductor device such as an LSI, as described above. However, there is a limit in lithography techniques. Although an increase in drain current has been studied by using methods different from lithography techniques, theses methods are associated with crystal defects and an increased cost because of a new manufacturing system.
High speed and an increase in drain current have been studied also for a peripheral circuit similar to memories and arithmetic and logical units. FIG. 5 shows the layout of p-channel field effect transistors disposed in a lattice shape and partially constituting a semiconductor device. This plan layout of p-channel field effect transistors is often used in a peripheral circuit of a CMOS device such as a PLL oscillator. However, as the integration degree becomes high, drain current of p-channel field effect transistors having this plan layout is reduced as compared to the design value and the total performance of the semiconductor device is degraded.